A number of techniques are known to increase the performance and integration density of integrated circuits. Considerable increases of integration density have recently been achieved mainly by decreasing photolithographic defect densities. The use of electron and X-ray exposure methods instead of the hitherto used light radiation provides higher optical resolution. Techniques to reach very narrow line widths in the 1 .mu.m range and less by extending conventional lithographic processes while avoiding the cost-intensive techniques of electron and X-ray lithography are also known. With the technique of plasma or reactive ion etching for etching metals, semiconductive and dielectric materials further developments have occurred in the direction of very narrow widths, and consequently toward increased performance and integration density.
A number of publications and patents describe the so-called sidewall technology by means of which structures in the sub-micromater range can be made. In IEEE Electron Device Letters, Vol. EDL2, No. 1, January 1981, pp. 4 to 6, a method is described where vertical (anisotropic) dry etching methods are applied for making MOSFETs which are defined by an edge and have dimensions in the sub-micrometer range. The technology described permits the production of physical channel lengths of the MOSFETs in the 0.1 to 0.15 .mu.m range.
U.S. Pat. No. 4,358,340 describes a method of making sub-micrometer devices, but without using the sub-micrometer lithography, where a conductive thin film with dimensions in the sub-micrometer range is deposited across a vertical step between adjacent surfaces of an isolation, and subsequently vertically etched until there only remains that part of the conductive film which is adjacent the vertical step. The remaining isolation not covered by the conductor is removed, thus obtaining a gate of an MOS field effect transistor with a width in the sub-micrometer range which equals the layer thickness of the originally applied thin film.
U.S. Pat. No. 4,209,349 describes a method of forming very small mask openings for making semiconductor circuit arrangements. According to this method, first insulator regions are formed on a substrate so that substantially horizontal as well as substantially vertical surfaces are obtained. A second insulator layer is applied thereon of a material different from that of the first insulator layer, and it is subjected to a reactive ion etching process in such a manner that the horizontal regions of the second insulator layer are removed, with merely very narrow regions of this layer remaining on the vertical surface regions of the first insulator layer, and the respective regions of the substrate, respectively. Subsequently, the exposed substrate regions are thermally oxidized, and for finally forming the desired mask openings the regions of the second insulating layer there are removed. By means of this method, minimum dimensions smaller than those of hitherto applied photolithographic methods are to be obtained.
In the process of U.S. Pat. No. 4,209,349, the first insulator layer (silicon dioxide) determines the position and thickness of the mask (column 2, line 62). All openings in the insulator layer are made by standard photolithography and etching techniques (column 3, line 21) according to which no vertical sidewalls can be made. In the method as disclosed by the invention, however, a polymeric layer determines position and thickness of the mask. In the method of the U.S. patent, only hot processes are applied, e.g., the chemical vapor deposition of silicon nitride at approximately 1000.degree. C. (column 5, line 69), whereas in the method as disclosed by the invention so-called cold processes at less than 300.degree. C. are performed permitting a more universal application of the method. With the method of the U.S. patent, masks with a layer thickness of less than 0.5 .mu.m can be made which are not suitable as masks, e.g., for etching deep trenches. With the method as disclosed by this patent, however, masks with a thickness of 2 to 3 .mu.m can be made that can be used for etching 4 to 5 .mu.m deep trenches in a silicon substrate. From thermal oxidation (column 4, line 64 of the U.S. patent), there results an asymmetrical mask with the bird's beak problem being involved which originates from the forming of a non-planar silicon dioxide on the trench surface, so that the mask cannot be used for trench etching also for that reason. The mask made in accordance with the invention has strictly vertical sidewalls and is of a symmetrical structure.
A feature common to all these known methods is that for making structures with vertical sidewalls and dimensions in the sub-micrometer range materials as polysilicon, silicon nitride or silicon dioxide are used which are all deposited at higher temperatures. Problems associated with high temperature fabrication are well documented in this field.
Another problem in the process of sidewall image transfer is the difficulty of avoiding etching into the underlying layer upon which a spacer is formed. This can be explained by referring to FIGS. 1 and 2. Basically, as illustrated in FIG. 1A, the vertical step is first etched into some material and then as illustrated in FIG. 1B, a conformal layer of another material, a spacer material is deposited over the first material. By the use of reactive ion etching (RIE), etching of the space material is done anisotropically. This results in a leftover spacer of a second material formed against the edge of the step material. Such is illustrated in FIG. 1C.
The step material is then removed as illustrated in FIG. 1D such that only the spacer, now free standing remains. This is illustrated in FIG. 1D. The free standing spacer can then be used as a mask to etch away an underlying layer as illustrated in FIG. 1E.
This technique, while broadly demonstrated, has problems in terms of the selectivity of the etch of the spacer to the material immediately below it. There are a limited number of materials and RIE etch gases and therefore it is difficult to avoid etching into the underlying layer as the spacer is formed. FIG. 2A illustrates an idea or technique where etching of the spacer material stops at the material beneath it. In FIG. 2A, the dotted line indicates the original thickness of the spacer material with the arrows indicative of the ideal depth of etch. Such ideally, therefore, conforms to that illustrated in FIG. 1C. In fact, however, the etch, usually CF.sub.4, causes a step or offset from one side of the spacer to the other side in the underlying layer. Such is illustrated in FIG. 2B. The step occurs because one side of the spacer is covered by the step material, but the other side is exposed to the etching. The problem is exacerbated by the need for longer over-etch times as nonuniformity of the RIE system and spacer material deposition system occurs. When the step material is removed, the resulting structure is illustrated in FIG. 2C. Thus, when the step material is removed, the offset will be propagated into whatever layer is beneath the underlying material. This occurs as the underlying material is etched with one side being thicker than other other. The offset is illustrated in FIG. 2D.
For purposes of illustration, example is the fabrication of an FET. The underlying layer is SiO.sub.2 with polysilicon directly beneath it. Disposed beneath the polysilicon layer is a thin, approximately 140 angstroms, gate oxide. Given the known technology as one side of the polysilicon completes the etch cycle, the other side does not. Thus, over-etching begins to cutoff the gate oxide. The gate oxide is etched through, the silicon beneath is etched quickly. The result is an asymmetry in the device. Such is illustrated in FIGS. 2E and 2F.
Technology that addresses this problem is represented by U.S. Pat. Nos. 4,432,132 and 4,449,287. In neither, however, is the problem of avoiding the deep or offset effectively dealt with. Other technology directed more broadly to sub-micron technology is represented by U.S. Pat. Nos. 4,093,503, 4,354,896, and 4,385,975. While generally of interest, those references also do not solve the problem set forth and explained relative to FIG. 2.